1. Technical Field
The present application relates generally to an improved integrated circuit apparatus and method. More specifically, the present application is directed to a duty cycle measurement apparatus and method.
2. Description of Related Art
The speed at which modern integrated circuit devices, such as microprocessors or systems-on-a-chip, operate has been greatly increasing in recent years. With such high speed devices variations in duty cycle, i.e. the ratio of pulse duration to a pulse period, may cause performance degradation if a mid-cycle edge is used. Moreover, variations in duty cycle may limit functionality if the clocked circuits depend upon minimum up or down time of the clock cycle, e.g., dynamic circuits.
Duty cycle is sensitive to many different factors including operating frequency, operating temperature, supply voltage, circuit design style, circuit loading, and process (e.g., variations in the doping, threshold voltage, mobility, gate oxide thickness, etc. across single and/or multiple wafers). Because so many different factors may affect duty cycle, it is important to be able to accurately measure clock duty cycle at the point of use on the chip under actual operating conditions.
However, limitations on bandwidth of off-chip connections generally constrain practical measurement to a few hundred MHz. This is at least an order of magnitude lower frequency than the frequency at which current integrated circuit devices, e.g., microprocessors or systems-on-a-chip, operate. Thus, due to limitations of off-chip connections, it is very difficult to obtain accurate measurements of clock duty cycle at the point of use on the chip under actual operating conditions.